%%
%%
%%
%%
%%April10,2001
%%Copyright1994-2009TheMathWorks,Inc.
%%
%%Disclaimer
%%==========
%%
%%ThefunctionalityprovidedinthisTLCmoduleiscurrentlyunder
%%development.
%%
%%Nomenclature
%%============
%%
%%?Linesandwordsmarkedwiththequestionmarkaresubjecttodiscussion,
%%changeorgeneralnotsettledatthispointintime
%%
%%iLinesleadedby"i"markingMathworksinternalfieldsthatshouldnot
%%beusedbyacustomer
%%
%%Syntax
%%======
%%
%%Subsystem-Sybsystemorrootlevelsystem
%%
%%Abstract
%%========
%%
%%TheBlockHierarchyMapprovidesainmemoryrepresentationofthe
%%graphicalmodel.
%%
%%Notethattherearetwoblockdiagramparametersthatcontrolwhether
%%virtualblocksandregionsarewritenintoBlockHierarchyMap:
%%'IncludeVirtualBlocksInRTWFileBlockHierarchyMap'
%%'IncludeRegionsInRTWFileBlockHierarchyMap'
%%Bydefaultthesetwoparametersare'off'.
%%
%%BlockHierarchyMap{
%%NumSubsystems-Numberofnoderecordsinthe
%%
%%Subsystem{
%%Name-Mangledsubsystemname
%%SLName-Unmangledsubsystemname
%%
%%SubsystemBlkIndex-[Subsystemindex,Blockindex]backreference
%%tothesubsystemblockinthe
%%BlockHierarchyMap
%%
%%Type-Subsystemtype(root,enable,trigger,fcncall
%%action,virtual)
%%MaskType-empty("")ifnotmaskotherwisemasktype
%%ChildSubsystems-Vectorofsubsystemindicesthatincludeall
%%childsubsystemblocks
%%ChildSubsystemBlks-Vectorofblockindicesthatincludeall
%%childsubsystemblocks
%%InputPortBlocks-Vectorofindicesthatincludeallinputport
%%blocks
%%OutputPortBlocks-Vectorofindicesthatincludealloutputport
%%blocks
%%DataStoreBlocks-Vectorofindicesthatincludealldatastore
%%memoryblocks
%%NumBlocks-NumberofBlocks
%%Block{
%%Name-Mangledblockname
%%SLName-Unmangledblockname
%%Type-BlockTypeincludessubsystems,inputandoutput
%%portblocks
%%Virtual[0,1,2]-(no,yes,pcv)pcv...postcompilevirtual
%%
%%i_blkref-[systemidx,instanceidx,blockidx]
%%iThisfieldisforinternalusageonly.Alibrary
%%ifunctionwillbeprovidedthatreturnsthereal
%%iblockrecord([-1,-1,-1]forvirtualorpcv)
%%NumDataOutputPorts-Numberofdataoutputports
%%NumDataInputPorts-Numberofdatainputports
%%NumControlInputPorts
%%-Numberofcontrol(enable,trigger,fcn-call)
%%inputports
%%
%%DataOutputPort{
%%Name-Mangledportname
%%SLName-Unmangledportname
%%SignalLabel-Labelofthesignallineconnected
%%totheoutputport
%%Connected-(no,yes,partial)or(0,1,2)
%%TestPoint-1iftheusermarkedtheoutputportasa
%%testpoint(0otherwise)
%%NumRegions-Numberofcontiguousmemoryregions
%%
%%Region{
%%MemoryMapIdx-Indexintotheglobalmemorymap
%%Informationaboutdatatype,dimension,...
%%canbereadfromtheglobalmemorymap
%%_Source-Theactualsourceofthissignal
%%Offset-nonzeroifconnectedtoamergeblock
%%Length-lengthofthecontiguousmemoryregion
%%Dimensions
%%Connected-(no,yes)or(0,1)
%%FunctionArgumentIdx
%%-(Forreusedfunctioninputoroutput)index
%%ofcanonicalinputoroutputinthefunction
%%argumentlist.OnlysupportedforERTtarget
%%}
%%
%%DataInputPort{-samecontentsasDataOutputPort
%%}
%%
%%ControlInputPort{-samecontentsasDataOutputPort
%%}
%%
%%NumParameters
%%Parameter{
%%Name-Mangledparametername
%%IsReference-(no,yes)or(0,1)isreferencesbya
%%workspaceormaskvariable
%%MemoryMapIdx
%%}
%%
%%NumContStates
%%ContState{
%%Name-Namedcontinuesstate
%%Dimensions
%%MemoryMapIdx
%%}
%%
%%NumDiscStates
%%DiscState{
%%Name-Nameddiscretestate
%%Dimensions
%%MemoryMapIdx
%%}
%%
%%NumDerivatives
%%Derivative{
%%Name-empty
%%Dimensions
%%MemoryMapIdx
%%}
%%
%%NumDataStores-nonzeroifdatastorememoryblock
%%DataStore{
%%Name-Nameofthedatastore
%%SLName-
%%MemoryName-
%%Dimenstion
%%MemoryMapIdx
%%}
%%
%%}%%endofBlock
%%}%%endofSubsystem
%%#ifGenerateBusHierarchy
%%|NumSignalHierarchyDescriptors-NumberofSignalHierarchyDescriptors
%%|SignalHierarchyDescriptor{-EquivalentofaBlockrecord
%%|#ifBlockexistsinBHM
%%|GrSrc-TheBlockHierarchyMapindexthatcorrespondstothisSHD
%%|#else
%%|FullBlockPath-ThefullmangledblockpathforablockthatdoesnotexistinBHM
%%|#endif
%%|OutputPortIdx-OutputportindexoftheblockthatthisSHDbelongsto
%%|Type-BlockTypeincludessubsystems,inputandoutput
%%|portblocks
%%|Virtual[0,1,2]-(no,yes,pcv)pcv...postcompilevirtual
%%|Synthesized[0,1]-(no,yes)Istheblocksynthesized?Synthesizedblockswillnot
%%|appearinBHM
%%|i_blkref-[systemidx,instanceidx,blockidx]
%%|iThisfieldisforinternalusageonly.Alibrary
%%|ifunctionwillbeprovidedthatreturnsthereal
%%|iblockrecord([-1,-1,-1]forvirtualorpcv)
%%|NumHierarchyNodes-Currently,thereisalwaysoneHierarchyNodeperSHD
%%|HierarchyNode{-EquivalentofaDataOutputPortrecordforablock
%%|Thisnodecorrespondstoanodeinthebushierarchy.If
%%|thenodeisasubbus,aRegionrecordisgeneratedforeach
%%|componentsignal(whichpointstotheshdIdxthat
%%|describesthatcomponent).Otherwise,asingleRegionis
%%|generatedthathasSource,DimensionsandOffsetinformation.
%%|SignalLabel-Nameofthissignal
%%|#ifNumRegions>1
%%||NumRegions-Numberofregions
%%||Region{
%%||#ifRegionisasubbus
%%|||Type-Setto"Bus"
%%|||SigHierIdx-shdIdx.IndexintotheSignalHierarchyDescriptor
%%|||recordthatdescribesthissubbussignal
%%||#else
%%|||Type-Setto"Region"
%%|||SigHierIdx-shdIdx.IndexintotheSignalHierarchyDescriptor
%%|||recordthatdescribesthisleafsignal
%%||#endif
%%||}
%%|#else
%%||Region{
%%||MemoryMapIdx-Indexintotheglobalmemorymap
%%||Informationaboutdatatype,dimension,...
%%||canbereadfromtheglobalmemorymap
%%||_Source-Theactualsourceofthissignal
%%||Offset-nonzero=>actualsource=_Source+offset
%%||Length-lengthofthecontiguousmemoryregion
%%||Dimensions
%%||Connected-(no,yes)or(0,1)
%%||FunctionInputIdx
%%||-Forreusedsubsysteminputport
%%||}
%%|#endif
%%|}%endofHierarchyNode
%%|}%endofSignalHierarchyDescriptor
%%#endif
%%}%%endofBlockHierarchyMap
%%
%%
%if EXISTS("_GRAPHMAPLIB_") == 0
%assign _GRAPHMAPLIB_ = 1
%<LibAddToCompiledModel("BlockHierarchyMapGenerated", 0)>
 
%%Function:FcnMapBlockHierarchy=============================================
%%Abstract:
%%Mapstheblockhierarchymaptotheglobalmememorymap.
%%
%function FcnMapBlockHierarchy() void
  %with ::CompiledModel
    %if BlockHierarchyMapGenerated == 0
      %with BlockHierarchyMap
        %foreach sybsysIdx = NumSubsystems
          %with Subsystem[sybsysIdx]
            %foreach blkIdx = NumBlocks
              %with Block[blkIdx]
                %foreach portIdx = NumDataInputPorts
                  %<FcnMapPort(DataInputPort[portIdx])>
                %endforeach
                %foreach portIdx = NumControlInputPorts
                  %<FcnMapPort(ControlInputPort[portIdx])>
                %endforeach
                %foreach portIdx = NumDataOutputPorts
                  %<FcnMapPort(DataOutputPort[portIdx])>
                %endforeach
                %foreach paraIdx = NumParameters
                  %<FcnMapParameter(Parameter[paraIdx])>
                %endforeach
                %foreach dstateIdx = NumDiscStates
                  %<FcnMapDState(DiscState[dstateIdx])>
                %endforeach
                %foreach cstateIdx = NumContStates
                  %<FcnMapCState(ContState[cstateIdx])>
                %endforeach
                %foreach cderivIdx = NumDerivatives
                  %<FcnMapCStateDerivatives(Derivative[cderivIdx])>
                %endforeach
                %foreach dstoreIdx = NumDataStores
                  %<FcnMapDStore(DataStore[dstoreIdx])>
                %endforeach
              %endwith
            %endforeach
          %endwith
        %endforeach
         
        %assign useDatasetLoggingHier = TLC_FALSE
        %if IsModelReferenceSimTarget() && EXISTS(NumSignalHierLoggingInfo) && (NumSignalHierLoggingInfo > 0)
          %assign useDatasetLoggingHier = TLC_TRUE
        %endif
           
        %% Process any SignalHierarchyDescriptor records
        %if IsModelReferenceSimTarget() && !useDatasetLoggingHier && EXISTS(NumSignalHierarchyDescriptors)
          %foreach shdIdx = NumSignalHierarchyDescriptors
            %with SignalHierarchyDescriptor[shdIdx]
              %foreach hnIdx = NumHierarchyNodes
                %<FcnMapPortSigHier(HierarchyNode[hnIdx])>
              %endforeach
            %endwith
          %endforeach
        %endif
      %endwith %% BlockHierarchyMap
      %assign ::CompiledModel.BlockHierarchyMapGenerated = 1
    %endif %% BlockHierarchyMapGenerated == 0
  %endwith %% ::CompiledModel
%endfunction
 
%%Function:SLibSystemBlockExist=============================================
%%Abstract:
%%Returnstrueifthereaonetoonemappingfromablockrecordinthe
%%blockhierarchymaptoablockrecordintheSystemsrecordexist.
%%
%function SLibSystemBlockExist(grBlock) void
  %return (ISFIELD(grBlock, "_blkref") && grBlock._blkref[2] != -1) ? ...
    TLC_TRUE : TLC_FALSE
%endfunction
 
%%Function:SLibGraphicalBlockExist==========================================
%%Abstract:
%%Returnstrueifthereaonetoonemappingfromablockrecordinthe
%%Systemsrecordtoablockrecordinblockhierarchymaptheexist.
%%
%function SLibGraphicalBlockExist(block) void
  %return (ISFIELD(block, "GrSrc") && block.GrSrc[1] != -1) ? ...
    TLC_TRUE : TLC_FALSE
%endfunction
 
%%Function:SLibGetGraphicalBlockIdx=========================================
%%Abstract:
%%ThisfunctionreturnsthegraphicalblockindexforSystemblockrecord.
%%
%%Example:
%%
%%%ifSLibGraphicalBlockExist(block)
%%%assigngrBlockIndex=SLibGetGraphicalBlockIdx(block)
%%%with::CompiledModel.BlockHierarchyMap
%%%assigngrSubSys=Subsystem[grBlockIndex[0]]
%%%assigngrBlock=grSubSys.Block[grBlockIndex[1]]
%%%endwith
%%%endif
%%
%function SLibGetGraphicalBlockIdx(block) void
  %return ISFIELD(block, "GrSrc") ? block.GrSrc : [-1, -1]
%endfunction
 
%%Function:SLibGetSystemBlockIdx============================================
%%Abstract:
%%Thisfunctionreturnsthesystemblockindexforblockhierarchymapblock
%%record.
%%
%%Example:
%%
%%%ifSLibSystemBlockExist(grBlock)
%%%assignblockIndex=SLibGetSystemBlockIdx(grBlock)
%%%with::CompiledModel
%%%assignsystem=System[blockIndex[0]]
%%%assignblock=system.Block[blockIndex[2]]
%%%endwith
%%%endif
%%
%function SLibGetSystemBlockIdx(grBlock) void
  %return ISFIELD(grBlock, "_blkref") ? grBlock._blkref : [-1, -1, -1]
%endfunction
 
%%Function:FcnMapPort=======================================================
%%Abstract:
%%Mapsaportobjecttotheglobalmemorymap.
%%
%function FcnMapPort(port) void
  %assign portObj = SLibCreateDummyPortRecord()
  %with port
    %if IsModelReferenceSimTarget()
      %% Support bus hierarchy
      %foreach regIdx = NumRegions
        %with Region[regIdx]
          %if (Type == "Bus" || !ISEMPTY("SigHierIdx"))
            %continue
          %endif
          %assign portObj.SignalSrc = _Source
          %assign sigRec = SLibGetSourceRecord(portObj, 0)
          %if !ISEMPTY(sigRec) %% grounded or function call
            %assign Region[regIdx].MemoryMapIdx = sigRec.MemoryMapIdx
          %endif
        %endwith %% Region[regIdx]
      %endforeach %% regIdx = NumRegions
    %else %% Bus hierarchy
      %foreach regIdx = NumRegions
        %assign portObj.SignalSrc = Region[regIdx]._Source
        %assign sigRec = SLibGetSourceRecord(portObj, 0)
        %if !ISEMPTY(sigRec) %% grounded or function call
          %assign Region[regIdx].MemoryMapIdx = sigRec.MemoryMapIdx
        %endif
      %endforeach
    %endif %% Bus hierarchy
  %endwith %% port
%endfunction
 
%%Function:FcnMapPortSigHier================================================
%%Abstract:
%%Mapsaportobjecttotheglobalmemorymap.WorkswiththeHierarchyNodes
%%
%function FcnMapPortSigHier(sigHierNode) void
  %assign portObj = SLibCreateDummyPortRecord()
  %with sigHierNode
      %% Support bus hierarchy
      %foreach regIdx = NumRegions
        %with Region[regIdx]
          %if (!ISEMPTY("SigHierIdx"))
            %continue
          %endif
          %assign portObj.SignalSrc = _Source
          %assign sigRec = SLibGetSourceRecord(portObj, 0)
          %if !ISEMPTY(sigRec) %% grounded or function call
            %assign Region[regIdx].MemoryMapIdx = sigRec.MemoryMapIdx
          %endif
        %endwith %% Region[regIdx]
      %endforeach %% regIdx = NumRegions
  %endwith
%endfunction
 
%%Function:FcnMapParameter==================================================
%%Abstract:
%%Mapsaparameterobjecttotheglobalmemorymap.
%%
%function FcnMapParameter(parameter) void
  %if parameter._idx > -1 %% post compile virtual blocks
    %assign parameter.MemoryMapIdx = ...
      ModelParameters.Parameter[parameter._idx].MemoryMapIdx
  %endif
%endfunction
 
%%Function:FcnMapDState=====================================================
%%Abstract:
%%Mapsadiscretestateobjecttotheglobalmemorymap.
%%
%function FcnMapDState(dstate) void
  %if dstate._idx > -1 %% post compile virtual blocks
    %assign dstate.MemoryMapIdx = ...
      ::CompiledModel.DWorks.DWork[dstate._idx].MemoryMapIdx
  %endif
%endfunction
 
%%Function:FcnMapCState=====================================================
%%Abstract:
%%MapsaContinuousstateobjecttotheglobalmemorymap.
%%
%function FcnMapCState(cstate) void
  %assign cstate.MemoryMapIdx = ...
    ::CompiledModel.ContStates.ContState[cstate._idx].MemoryMapIdx
%endfunction
 
%%Function:FcnMapCStateDerivatives=========================================
%%Abstract:
%%MapsaContinuousstateobjecttotheglobalmemorymap.
%%
%function FcnMapCStateDerivatives(cderiv) void
  %assign cderiv.MemoryMapIdx = ...
    ::CompiledModel.ContStates.ContState[cderiv._idx].DerivativeMemoryMapIdx
%endfunction
 
%%Function:FcnMapDStore=====================================================
%%Abstract:
%%Mapsadatastorememoryblocktotheglobalmemorymap.
%%
%function FcnMapDStore(dstore) void
  %if dstore._idx > -1 %% post compile virtual blocks
    %assign dstore.MemoryMapIdx = ...
      ::CompiledModel.DWorks.DWork[dstore._idx].MemoryMapIdx
  %endif
%endfunction
 
 
%endif %% _GRAPHMAPLIB_
 
%%[EOF]graphmaplib.tlc